1. Field of the Invention
The present invention relates to solid-state image pickup devices for use in apparatuses, such as digital still cameras and digital camcorders.
2. Description of the Related Art
Recently, pixel-amplification-type solid-state image pickup devices, a type of solid-state image pickup devices, have been widely used in digital still cameras and digital camcorders because of their capability of achieving high image quality and high resolution. The more the number of pixels increases, the further each of the pixels is scaled down. Additionally, performance demanded for the solid-state image pickup devices is also increasing. Particularly, a decrease in power consumption is strictly demanded because it affects continuous use time of batteries. Japanese Patent Laid-Open No. 2005-217771 discloses a solid-state image pickup device having a power saving mode serving as a method for decreasing power consumption thereof.
The solid-state image pickup device according to Japanese Patent Laid-Open No. 2005-217771 includes a column amplifier unit for each pixel column. A storage capacitor is arranged at an output node of the column amplifier unit through a transfer metal oxide semiconductor (MOS) transistor. To decrease the power consumption, the solid-state image pickup device shuts off or decreases current flowing through the column amplifier unit during a non-operational period (hereinafter, referred to as an OFF period). As described above, the further the pixels are scaled down, the further transistors constituting the solid-state image pickup device and, thus, the transfer MOS transistor, are scaled down. When gate potential is equal to source potential, subthreshold current may unfortunately flow through the MOS transistor having a small gate length.
The method disclosed in Japanese Patent Laid-Open No. 2005-217771 may require further examination because off-state current flows when the transistor between the column amplifier unit and the storage capacitor storing a signal fed from the column amplifier unit is small. A mechanism thereof will be described in detail below.
In the method disclosed in Japanese Patent Laid-Open No. 2005-217771, potential at the output node of the column amplifier unit is equal to the highest potential (e.g., VDD) or the lowest potential (e.g., ground potential) while the current to the column amplifier unit is shut off.
When a transfer switch includes a P-channel MOS (PMOS) transistor, the voltage VDD is supplied to a gate of PMOS transistor during an OFF period thereof. If the potential at the output node of the column amplifier unit is equal to the voltage VDD in the power saving mode, source potential of the PMOS transistor is also equal to the voltage VDD and, thus, subthreshold current flows therethrough. When the transfer switch includes an N-channel MOS (NMOS) transistor, the ground voltage is supplied to a gate of the NMOS transistor during an OFF period. If the potential at the output node of the column amplifier unit is equal to the ground voltage in the power saving mode, source potential of the NMOS transistor is also equal to the ground potential and, thus, subthreshold current flows therethrough.
Since the subthreshold current causes the storage capacitor to release electrical charge stored therein and attenuates the stored signal, preferable image quality may be disadvantageously unavailable.